This invention relates to a programmable nonvolatile semiconductor memory device and more particularly to a flash memory whose addresses are selected in a multiple access to simultaneously select a plurality of blocks or word lines in a memory cell array and effect the erase, write and test operations.
Conventionally, as one type of a semiconductor memory device, electrically erasable and programmable read only memories (EEPROMs) are known. Among them, a NAND cell type EEPROM in which a plurality of memory cells are serially connected to constitute a NAND cell can be formed with high integration density and receives much attention.
One memory cell in the NAND cell type EEPROM has a MOSFET structure having a control gate and floating gate (charge storage layer) stacked above a semiconductor substrate with an insulating film disposed therebetween. A plurality of memory cells are serially connected to form a NAND cell with a source/drain commonly used by every two adjacent memory cells. The NAND cells are arranged in a matrix form to constitute a memory cell array.
Drains lying on one side of the NAND cells arranged in the column direction in the memory cell array are commonly connected to a bit line via selection gate transistors and sources thereof on the other side are connected to a common source line via other selection gate transistors. The control gate electrodes of the memory cell transistors and the gate electrodes of the above selection gate transistors are respectively connected to word lines (control gate lines) and selection gate lines formed to extend in the row direction of the memory cell array.
As a known example of the conventional NAND cell type EEPROM, a document (paper) 1; K. -D. Suh et al., "A 3.3 V 32 Mb NAND Flash Memory With Incremental Step Pulse Programming Scheme", IEEE J. Solid-State Circuits, vol. 30, pp. 1149-1156, November 1995 and a document (paper) 2; Y. Iwata et al., "A 35 ns Cycle Time 3.3 V Only 32 Mb NAND Flash EEPROM", IEEE J. Solid-State Circuits, vol. 30, pp. 1157-1164, November 1995 are published. In the document 1, the basic construction and operation of the conventional NAND cell type EEPROM are explained.
Recently, electronic still cameras (Solid State Camera) using the above-described NAND cell type EEPROM as a storage medium are commercialized. For example, DS-7 sold by KABUSHI KIKAISHA FUJI SHASHIN FILM is one example. The camera can take 30 photographs with 300,000 pixels by use of a 16 Mbit NAND type EEPROM. Therefore, in this case, it is understood that approx. 0.5 Mbit is used for each photograph. Since a erase block (sector) size is constructed by 32 kbits in the 16 Mbit NAND type EEPROM, 16 blocks are required in the photographs of 300,000 pixels. The electronic still camera has one of features that a photographed picture is checked in the photographed place and a photograph can be retaken as required. In the case of retake, data of 16 blocks and 0.5 Mbit is erased. At the time of erase, data of 16 blocks is erased for each block and it is necessary to effect the erase verify process for verifying whether or not the erase process of each block is sufficiently effected. For this reason, the erase time becomes long. For example, if the erase time for one block is 2 ms, then 32 ms is taken to erase data of 16 blocks and the photographing operation is limited during this time.
In order to reduce the erase time, a method for simultaneously erasing a plurality of blocks is proposed in a document 3; E. Harari et al., "EEPROM System with Erase Sector Select", U.S. Pat. No. 5,418,752, May 23, 1995. This technique is called a "Selective Multiple Sector Erase" and sectors (blocks) of the flash memory which are simultaneously erased can be selectively specified.
The method for simultaneously erasing a plurality of blocks is effected as indicated by the timing chart shown in FIG. 1. That is, first, a command CM1 for specifying a sector to be erased is input and a plurality of sets (in the case of FIG. 1, three sets are shown) of sector (block) addresses A8 to A15, A16 to A20 are input. Then, an erase command CM2 is input to erase a plurality of sectors specified by the sector (block) addresses in the period of tMBERASE. After the erase operation, a status reading command CM3 is input to read the erase verify state. It is confirmed by the erase verify reading operation that the threshold voltages of all of the memory cells in the selected sectors have become negative.
However, in the above multiple block erase method, sector (block) address registers (REG) 221, 223, . . . (refer to FIG. 3A in the document 3) for selectively specifying sectors to be erased are required for each sector (block) although a plurality of blocks can be simultaneously erased. For this reason, the chip size is increased and chip cost is raised because the additional register circuit portion is provided. Further, as described above, in order to selectively erase a plurality of sectors (blocks), it is necessary to input a plurality of sets of sector (block) addresses A8 to A15, A16 to A20 for specifying the sectors to be erased before the erase operation. The time for inputting a plurality of sets of sector (block) addresses A8 to A15, A16 to A20 and a complicated process such as a decoding process for the operation of inputting a plurality of addresses cannot be neglected.
As described above, in the conventional nonvolatile semiconductor memory device, since the erase operation and verify operation for each block are required, erase time becomes long when a plurality of blocks are erased. If a plurality of blocks are simultaneously erased in order to solve this problem, a sector (block) address register for selectively specifying the sector (block) to be erased is required for each sector (block) and the chip cost is raised. Further, it is necessary to take time for inputting an address to the register and the address inputting operation becomes complicated.
The above-described problems are not limited to the erase operation and may occur when a plurality of blocks in the memory cell array are simultaneously selected and written or when a test operation is effected.